Diodes AP7363 Manuel d'utilisateur télécharger pdf (Page 8)

AP7363

Document number: DS35059 Rev. 8 - 2

8 of 14

www.diodes.com

December 2012

P7363

Application Note (cont.)

Stability and Phase Margin

Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate phase margin, which is defined

as the difference between the phase shift and -180 degrees at the frequency where the loop gain crosses unity (0 dB). For most LDO regulators,

the ESR of the output capacitor is required to create a zero to add enough phase lead to ensure stable operation. The AP7363 has a internal

compensation circuit which maintains phase margin regardless of the ESR of the output capacitor, any type of capacitos can be used.

The two charts on the next page show the gain/phase plot of the AP7363 with an output of 1.2V, 10μF ceramic output capacitor, delivering 1.5A

load current and no load. It can be seen the phase margin is about 90° (which is very stable).

Short Circuit Protection

When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to

prevent over-current and to protect the regulator from damage due to overheating.

Thermal Shutdown Protection

Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing the device to cool down. When the

junction temperature reduces to approximately +160°C the output circuitry is enabled again. Depending on power dissipation, thermal resistance,

and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the heat dissipation of the regulator, protecting it

from damage due to overheating.

Low Quiescent Current

The AP7363, consuming only around 0.5mA for all input range, provides great power saving in portable and low power applications.

Output Noise

This is the integrated value of the output noise over a specified frequency range. Input voltage and output load current are kept constant during

the measurement. Results are expressed in µVrms or µV√Hz.

The AP7363 is a low noise regulator and needs no external noise reduction capacitor. Output voltage noise is typically 100μVrms overall noise

level between 100 Hz and 100 kHz.

Noise is specified in two ways:

Output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz

bandwidth). This type of noise is usually plotted on a curve as a function of frequency.

Output noise voltage is the RMS sum of spot noise over a specified bandwidth. Spot noise is measured in units μV/√Hz or nV/√Hz and total

output noise is measured in μV(rms). The primary source of noise in low-dropout regulators is the internal reference.

-120

-100

-80

-60

-40

-20

100

120

FREQUENCY(Hz)

Gain-Bandwidth Plot for 1.5A Load

140

100

120

100

-20

-40

-60

-80

PHASE MARGIN (°)

1k 10k 100k 1M

PHASE

V = 2.7V

V = 1.2V

I = 1.5A

C = 10µF CER

OUT

GAIN

AIN (dB)

-120

-100

-80

-60

-40

-20

100

120

(dB)

140

120

100

-20

-40

-60

-80

PHASE MARGIN (°)

FREQUENCY(Hz)

Gain-Bandwidth Plot for no Load

100 1k 10k 100k 1M

V = 2.7V

V = 1.2V

I = 0A

C = 10µF CER

OUT

PHASE

GAIN

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Commentaires sur ces manuels

Pas de commentaire

Diodes AP7363 Manuel d'utilisateur Page 8

Commentaires sur ces manuels

Produits connexes et manuels pour Matériel Diodes AP7363