Diodes AP3440 Manuel d'utilisateur télécharger pdf (Page 12)

AP3440

Document number: DS36691 Rev. 2 - 2

12 of 15

www.diodes.com

March 2014

AP3440

A Product Line of

Diodes Incorporated

NEW P RODUC T

Application Note (Cont.)

Compensation

The output capacitor and the load resistance largely determine where the error amplifier poles and zeros need to be placed for optimum transient

response and loop stability. The corner frequency of the pole and zero generated by output capacitor are:

OUTLOAD







………………………..(13)

OUTESR







………………………. .. (14)

Where R

LOAD

is the load resistance, C

OUT

is the output capacitance and R

ESR

is the capacitor ESR.

The error amplifier provides most of the loop gain. After selecting the output capacitor, the control loop is compensated by tailoring the frequency

response of the error amplifier. The low frequency pole of the error amplifier is the dominant pole and is determined primarily by C

COMP

and the

output resistance of the error amplifier as shown by:

COMPEAOUT







…………………..(15)

Resistor R

COMP

adds a zero to the frequency response to control gain in the mid frequency range. This zero frequency is:

COMPCOMP







……………………..(16)

Where R

COMP

and C

COMP

are compensation resistor and capacitor connected to COMP pin, R

OUT

is the output impedance of the error amplifier.

A 7.5kΩ resistor and 2.7nF capacitor are used in typical application.

Layout Consideration

PCB layout is very important to the performance of AP3440. The loop which switching current flows through should be kept as short as possible.

The external components (especially C

) should be placed as close to the IC as possible.

The feedback trace should be routed far away from the inductor and noisy power traces, and it needs to be routed as direct as possible. Locate

the feedback divider resistor network near the feedback pin with short leads.

Since the SW connection is the switching node, the output inductor should be located very close to the SW pins, and the area of the PCB

conductor is minimized to prevent excessive capacitive coupling.

The boot capacitor must also be located close to the device. The sensitive analog ground connections for the feedback voltage divider,

compensation components, slow start capacitor and frequency set resistor should be connected to a separate analog ground trace.

The RT/CLK pin is sensitive to noise so the R

resistor should be located as close as possible to the IC and routed with minimal lengths of trace.

Figure 6. Top View of PCB Layout Figure 7. Bottom View of PCB Layout

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Diodes AP3440 Manuel d'utilisateur Page 12

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